1. Field of the Invention
The present invention relates to a memory device including a semiconductor.
2. Description of the Related Art
A 1T1C DRAM which includes a memory cell including one transistor and one capacitor has no limit on the number of times of writing in principle, and can perform writing and reading at relatively high speed, thereby used in many kinds of electronic appliances (see Patent Document 1 and Patent Document 4). The 1T1C DRAM performs data reading in such a manner that accumulated charge is released to a bit line and a change in a potential is measured; therefore, the capacitance of the capacitor needs to be at a certain value or more. As a result, it becomes more and more difficult to keep necessary capacitance because of miniaturization of a circuit.
In contrast, in a gain cell DRAM which includes a memory cell including two transistors and one capacitor, an amount of charge can be amplified by a read transistor and the charge can be supplied to a bit line even when the capacitance of the capacitor is small; therefore, it is assumed that the capacitor can be made small (see Patent Document 2 and Patent Document 3).
FIG. 2 is a circuit diagram of a memory cell of a conventional gain cell DRAM. A memory cell 201 includes a write transistor 202 and a capacitor 203. A gate of the write transistor 202 is connected to a write word line 204. A drain of the write transistor 202 is connected to a bit line 205, a source of the write transistor 202 is connected to a first electrode (capacitor electrode) of the capacitor 203, and a second electrode of the capacitor 203 is connected to a read word line 208.
The source of the write transistor 202 and the first electrode of the capacitor 203 are connected to a gate of a read transistor 207. Further, a drain of the read transistor 207 is connected to the bit line 205 and a source of the read transistor 207 is connected to a source line 206.
In order that data is written in the memory cell 201, while a potential of the bit line 205 is at a value corresponding to the data, a potential of the write word line 204 is controlled so that the write transistor 202 is turned on; thus, the capacitor 203 is charged. Then, the potential of the write word line 204 is controlled, so that the write transistor 202 is turned off. At this time, a potential of a connection point (storage node SN) between the source of the write transistor 202 and the first electrode of the capacitor 203 has the value corresponding to the data.
In order that data is read from the memory cell 201, the bit line 205 is set to be in a floating state at a certain potential and a potential of the read word line 208 is controlled, so that the potential of the storage node SN is adjusted; thus, the state of the read transistor 207 is changed. At this time, when the read transistor 207 is on, the amount of charge accumulated in the bit line 205 is changed and the change in the potential of the bit line 205 is measured.